Performance Evaluation of a Reconfigurable, Embedded Photonic Multiring Interconnection Network

The ever increasing demand for interconnect bandwidth in embedded parallel processors has motivated the development of photonic communications technologies that effectively support short-distance links. Electrooptical I/O to and from VLSI chips is one such photonic technology. A multiring architecture that exploits optical I/O on and off chip is described in [1]. At the heart of the system is a VLSI photonic device based on the use of an M M × array of Vertical Cavity Surface Emitting Laser (VCSEL) and detector pairs [2]. Each VCSEL-detector pair is capable of operating at rates exceeding 1 Gb/s. With 32 = M , the raw bandwidth deliverable is greater than 1 Tb/s. In this paper we are interested in investigating the performance gains achievable on a class of embedded signal processing algorithms through the use of reconfiguration in the processor interconnection network. The application class is the set of pipelined problems in which computation and communication occurs on a cyclic basis. An example, synthetic aperture radar (SAR) image formulation, is shown below: In the SAR application, the first communication phase consists of data being input from the sensor array (a broadcast). The first computation phase consists of range processing. The second communication phase is a corner turn operation (an all-to-all pattern). The second computation phase is azimuth processing, and the final communication phase is the output of formulated SAR images (a reduction). RECONFIGURABLE MULTIRING ARCHITECTURE The multiprocessor interconnect described in [1] utilizes a multiring topology. Consider the four-node example where each processing node is connected to the multiring as illustrated below. Given the numerous VCSEL-detector pairs, we can assign disjoint subset of VCSEL-detector pairs to each processing node. If these subsets are allocated according to receiver designation, then each subset can be thought of as a channel associated with messages being received by a given node. By changing the number of VCSEL-detector pairs associated with each receiver, we can alter the bandwidth associated with that subring. Within a subring, media access is arbitrated using the Deficit Round Robin (DRR) fairness protocol [3], which supports the assignment of arbitrary bandwidth ratios to various sources on a subring. With the ability to set receiver bandwidth via the allocation of VCSELdetector pairs and the ability to set source bandwidth via the DRR media access protocol, the interconnect may be configured for arbitrary capacity (constrained by the total bandwidth available) for any potential flow (i.e., source-destination pair). * This material is based upon work supported by the DARPA VLSI Photonics Program under grant DAAL01-98-0074. Input Data Output Data Corner Turn Azimuth Processing Range Processing